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Parthasarathy P. Tirumalai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler
    Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:66-74 [Conf]
  2. Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry
    Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:287-295 [Conf]
  3. B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
    Code generation schema for modulo scheduled loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:158-169 [Conf]
  4. B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
    Register Allocation for Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 1992, pp:283-299 [Conf]
  5. Parthasarathy P. Tirumalai, M. Lee, Michael S. Schlansker
    Parallelization of loops with exits on pipelined architectures. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:200-212 [Conf]
  6. Parthasarathy P. Tirumalai, Jon T. Butler
    Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:2, pp:167-177 [Journal]

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