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Yasushi Yuminaka: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:8-15 [Conf]
  2. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Set-Valued Logic Networks for Wave-Parallel Computing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:277-282 [Conf]
  3. Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi
    Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:207-214 [Conf]
  4. Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:430-437 [Conf]
  5. Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi
    Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:54-60 [Conf]
  6. Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:210-215 [Conf]
  7. Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi
    Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:148-0 [Conf]

  8. Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. [Citation Graph (, )][DBLP]


  9. Equalization Techniques for Multiple-Valued Data Transmission and Their Application. [Citation Graph (, )][DBLP]


  10. Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. [Citation Graph (, )][DBLP]


  11. A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface. [Citation Graph (, )][DBLP]


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