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Andres Teene: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. R. Castagnetti, R. Venkatraman, B. Bartz, C. Monzel, T. Briscoe, Andres Teene, S. Ramesh
    A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:193-196 [Conf]
  2. Andres Teene, Bob Davis, R. Castagnetti, J. Brown, S. Ramesh
    Impact of Interconnect Process Variations on Memory Performance and Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:694-699 [Conf]

  3. Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. [Citation Graph (, )][DBLP]

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