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Nagarajan Ranganathan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Narender Hanchate, Nagarajan Ranganathan
    Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:92-97 [Conf]
  2. Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
    Control and Data Flow Graph Extraction for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:192- [Conf]
  3. Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate
    CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:329-334 [Conf]
  4. Narender Hanchate, Nagarajan Ranganathan
    Integrated Gate and Wire Sizing at Post Layout Level. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:225-232 [Conf]
  5. Narender Hanchate, Nagarajan Ranganathan
    Statistical Gate Sizing for Yield Enhancement at Post Layout Level. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:245-252 [Conf]
  6. Narender Hanchate, Nagarajan Ranganathan
    A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:228-233 [Conf]
  7. Narender Hanchate, Nagarajan Ranganathan
    A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:283-290 [Conf]
  8. Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi
    ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:745-748 [Conf]
  9. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1063-0 [Conf]
  10. Aswath Oruganti, Nagarajan Ranganathan
    Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:766-769 [Conf]
  11. Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu
    A VLSI ATM Switch Architecture for VBR Traffic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:420-427 [Conf]
  12. Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh
    An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:477-480 [Conf]
  13. Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan
    A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:215-220 [Conf]
  14. Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan
    VBR video traffic management using a predictor-based architecture. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2000, v:23, n:1, pp:62-70 [Journal]
  15. Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan
    Corner detection. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1990, v:23, n:11, pp:1223-1233 [Journal]
  16. Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan
    Gabor filter-based edge detection. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1992, v:25, n:12, pp:1479-1494 [Journal]
  17. Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan
    Efficient computation of gabor filter based multiresolution responses. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1994, v:27, n:7, pp:925-938 [Journal]
  18. Narender Hanchate, Nagarajan Ranganathan
    Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:8, pp:1011-1023 [Journal]
  19. V. Mahalingam, Nagarajan Ranganathan
    Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:12, pp:1523-1535 [Journal]
  20. Upavan Gupta, Nagarajan Ranganathan
    Multievent Crisis Management Using Noncooperative Multistep Games. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:577-589 [Journal]
  21. Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri
    A lossless image compression algorithm using variable block size segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Image Processing, 1995, v:4, n:10, pp:1396-1406 [Journal]
  22. Narender Hanchate, Nagarajan Ranganathan
    A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:711-739 [Journal]
  23. Narender Hanchate, Nagarajan Ranganathan
    LECTOR: a technique for leakage reduction in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:196-205 [Journal]
  24. Saraju P. Mohanty, Nagarajan Ranganathan
    A framework for energy and transient power reduction during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:562-572 [Journal]
  25. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:808-818 [Journal]
  26. Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa
    A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:1002-1012 [Journal]

  27. A linear programming formulation for security-aware gate sizing. [Citation Graph (, )][DBLP]


  28. Improving the reliability of on-chip L2 cache using redundancy. [Citation Graph (, )][DBLP]


  29. A microeconomic approach to multi-objective spatial clustering. [Citation Graph (, )][DBLP]


  30. An expected-utility based approach to variation aware VLSI optimization under scarce information. [Citation Graph (, )][DBLP]


  31. Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. [Citation Graph (, )][DBLP]


  32. A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. [Citation Graph (, )][DBLP]


  33. A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. [Citation Graph (, )][DBLP]


  34. A high speed systolic architecture for labeling connected components in an image. [Citation Graph (, )][DBLP]


  35. Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. [Citation Graph (, )][DBLP]


  36. RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. [Citation Graph (, )][DBLP]


  37. Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. [Citation Graph (, )][DBLP]


  38. A microeconomic approach to multi-robot team formation. [Citation Graph (, )][DBLP]


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