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Vivek Joshi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
    Logic SER Reduction through Flipflop Redesign. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:611-616 [Conf]

  2. Leakage power reduction using stress-enhanced layouts. [Citation Graph (, )][DBLP]


  3. Closed-form modeling of layout-dependent mechanical stress. [Citation Graph (, )][DBLP]


  4. Soft-edge flip-flops for improved timing yield: design and optimization. [Citation Graph (, )][DBLP]


  5. STEEL: a technique for stress-enhanced standard cell library design. [Citation Graph (, )][DBLP]


  6. Stress aware layout optimization. [Citation Graph (, )][DBLP]


  7. Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. [Citation Graph (, )][DBLP]


  8. IUF Scheduling Algorithm for Improving the Schedulability, Predictability and Sustainability of the Real Time System. [Citation Graph (, )][DBLP]


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