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Vivek Joshi:
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Publications of Author
- Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
Logic SER Reduction through Flipflop Redesign. [Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:611-616 [Conf]
Leakage power reduction using stress-enhanced layouts. [Citation Graph (, )][DBLP]
Closed-form modeling of layout-dependent mechanical stress. [Citation Graph (, )][DBLP]
Soft-edge flip-flops for improved timing yield: design and optimization. [Citation Graph (, )][DBLP]
STEEL: a technique for stress-enhanced standard cell library design. [Citation Graph (, )][DBLP]
Stress aware layout optimization. [Citation Graph (, )][DBLP]
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. [Citation Graph (, )][DBLP]
IUF Scheduling Algorithm for Improving the Schedulability, Predictability and Sustainability of the Real Time System. [Citation Graph (, )][DBLP]
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