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Shih-Hsien Lo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
    Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:410-415 [Conf]
  2. Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang
    High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:758-761 [Conf]

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