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Ajith Amerasekera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun
    A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:148-0 [Conf]
  2. Ajith Amerasekera
    Concurrent Optimization of Technology and Design for Nano CMOS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:27- [Conf]

  3. Ultra low power electronics in the next decade. [Citation Graph (, )][DBLP]


  4. The Changing Design Landscape. [Citation Graph (, )][DBLP]


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