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Guangyu Sun: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Guangyu Sun, Zhiqiang Gao, Yi Xu
    A Watermarking System for IP Protection by Buffer Insertion Technique. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:671-675 [Conf]
  2. Guangyu Sun, Johannes H. Voigt, Igor V. Filippov, Victor E. Marquez, Marc C. Nicklaus
    PROSIT: Pseudo-Rotational Online Service and Interactive Tool, Applied to a Conformational Survey of Nucleosides and Nucleotides. [Citation Graph (0, 0)][DBLP]
    Journal of Chemical Information and Modeling, 2004, v:44, n:5, pp:1752-1762 [Journal]
  3. Hongbin Zhang, Guangyu Sun
    Optimal Selection of Reference Set for the Nearest Neighbor Classification by Tabu Search. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2001, v:16, n:2, pp:126-136 [Journal]
  4. Hongbin Zhang, Guangyu Sun
    Feature selection using tabu search method. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2002, v:35, n:3, pp:701-711 [Journal]
  5. Hongbin Zhang, Guangyu Sun
    Optimal reference subset selection for nearest neighbor classification by tabu search. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 2002, v:35, n:7, pp:1481-1490 [Journal]

  6. A criticality-driven microarchitectural three dimensional (3D) floorplanner. [Citation Graph (, )][DBLP]

  7. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. [Citation Graph (, )][DBLP]

  8. Cost-driven 3D integration with interconnect layers. [Citation Graph (, )][DBLP]

  9. A Variation Aware High Level Synthesis Framework. [Citation Graph (, )][DBLP]

  10. Energy- and endurance-aware design of phase change memory caches. [Citation Graph (, )][DBLP]

  11. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. [Citation Graph (, )][DBLP]

  12. Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. [Citation Graph (, )][DBLP]

  13. Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. [Citation Graph (, )][DBLP]

  14. Arithmetic unit design using 180nm TSV-based 3D stacking technology. [Citation Graph (, )][DBLP]

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