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Publications of Author

1. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
   Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:299-304 [Conf]
   
2. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
   Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:383-388 [Conf]
   
3. Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
   High performance clock routing in X-architecture. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
4. 
   Gate planning during placement for gated clock network. [Citation Graph (, )][DBLP]
   
   
5. 
   Leakage power optimization for clock network using dual-Vth technology. [Citation Graph (, )][DBLP]
   
   
6. 
   Activity and register placement aware gated clock network design. [Citation Graph (, )][DBLP]
   
   
7. 
   Useful clock skew optimization under a multi-corner multi-mode design framework. [Citation Graph (, )][DBLP]