Search the dblp DataBase

Publications of Author

1. Sherif A. Tawfik, Volkan Kursun
   Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:73-78 [Conf]
   
2. Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
   Leakage-Aware Design of Nanometer SoC. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3231-3234 [Conf]
   
3. Sherif A. Tawfik, Volkan Kursun
   Multi-Vth Level Conversion Circuits for Multi-VDD Systems. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1397-1400 [Conf]
   
4. Sherif A. Tawfik, Volkan Kursun
   Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:645-648 [Conf]
   
5. Sherif A. Tawfik, Hossam A. H. Fahmy
   Algorithmic truncation of minimax polynomial coefficients. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
6. 
   Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. [Citation Graph (, )][DBLP]
   
   
7. 
   Low power and robust 7T dual-Vt SRAM circuit. [Citation Graph (, )][DBLP]
   
   
8. 
   Dynamic wordline voltage swing for low leakage and stable static memory banks. [Citation Graph (, )][DBLP]
   
   
9. 
   Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. [Citation Graph (, )][DBLP]
   
   
10. 
    Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. [Citation Graph (, )][DBLP]
    
    
11. 
    Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. [Citation Graph (, )][DBLP]
    
    
12. 
    Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. [Citation Graph (, )][DBLP]