The SCEAS System
Navigation Menu

Search the dblp DataBase


Madhu Mutyam: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K. Najeeb, Vishal Gupta, V. Kamakoti
    Delay and peak power minimization for on-chip buses using temporal redundancy. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:119-122 [Conf]
  2. Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Variation Analysis of CAM Cells. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:333-338 [Conf]
  3. Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie
    Delay and Energy Efficient Data Transmission for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:355-360 [Conf]
  4. Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin
    Investigating Simple Low Latency Reliable Multiported Register Files. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:375-382 [Conf]
  5. Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Compiler-directed thermal management for VLIW functional units. [Citation Graph (0, 0)][DBLP]
    LCTES, 2006, pp:163-172 [Conf]
  6. Madhu Mutyam, Kamala Krithivasan
    P Systems with Membrane Creation: Universality and Efficiency. [Citation Graph (0, 0)][DBLP]
    MCU, 2001, pp:276-287 [Conf]
  7. Madhu Mutyam
    Preventing Crosstalk Delay using Fibonacci Representation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:685-688 [Conf]
  8. P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam
    A Bus Encoding Technique for Power and Cross-talk Minimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:443-448 [Conf]
  9. Madhu Mutyam, Kamala Krithivasan
    Universality Results for Some Variants of P Systems. [Citation Graph (0, 0)][DBLP]
    WMP, 2000, pp:237-254 [Conf]
  10. Madhu Mutyam, Kamala Krithivasan
    A Survey of Some Variants of P Systems. [Citation Graph (0, 0)][DBLP]
    WMC-CdeA, 2002, pp:360-370 [Conf]
  11. Madhu Mutyam, Kamala Krithivasan
    Generalized normal form for rewriting P systems. [Citation Graph (0, 0)][DBLP]
    Acta Inf., 2002, v:38, n:10, pp:721-734 [Journal]
  12. Madhu Mutyam, Kamala Krithivasan
    Improved Results about Universality of P systems. [Citation Graph (0, 0)][DBLP]
    Bulletin of the EATCS, 2002, v:76, n:, pp:162-168 [Journal]
  13. Kamala Krithivasan, Madhu Mutyam
    Contextual P Systems. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:49, n:1-3, pp:179-189 [Journal]
  14. Madhu Mutyam, Kamala Krithivasan
    A Note on Hybrid P Systems. [Citation Graph (0, 0)][DBLP]
    Grammars, 2002, v:5, n:3, pp:239-244 [Journal]
  15. Madhu Mutyam, Kamala Krithivasan
    On a class of P automata. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Math., 2003, v:80, n:9, pp:1111-1120 [Journal]
  16. Madhu Mutyam
    Probabilistic Rewriting P Systems. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2003, v:14, n:1, pp:157-166 [Journal]
  17. M. Sakthi Balan, Kamala Krithivasan, Madhu Mutyam
    Some Variants in Communication of Parallel Communicating Pushdown Automata. [Citation Graph (0, 0)][DBLP]
    Journal of Automata, Languages and Combinatorics, 2003, v:8, n:3, pp:401-416 [Journal]
  18. Madhu Mutyam, Vaka Jaya Prakash, Kamala Krithivasan
    Rewriting Tissue P Systems. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:9, pp:1250-1271 [Journal]
  19. Rodica Ceterchi, Madhu Mutyam, Gheorghe Paun, K. G. Subramanian
    Array-rewriting P systems. [Citation Graph (0, 0)][DBLP]
    Natural Computing, 2003, v:2, n:3, pp:229-249 [Journal]
  20. Madhu Mutyam
    Rewriting P systems: improved hierarchies. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2005, v:334, n:1-3, pp:161-175 [Journal]
  21. Madhu Mutyam, Narayanan Vijaykrishnan
    Working with process variation aware caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1152-1157 [Conf]
  22. Nallamothu Satyanarayana, Madhu Mutyam, A. Vinaya Babu
    Exploiting on-chip data behavior for delay minimization. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:103-110 [Conf]
  23. Madhu Mutyam, Kamala Krithivasan, A. Siddhartha Reddy
    On Characterizing Recursively Enumerable Languages by Insertion Grammars. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2005, v:64, n:1-4, pp:317-324 [Journal]
  24. K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
    Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:425-436 [Journal]

  25. Block remap with turnoff: A variation-tolerant cache design technique. [Citation Graph (, )][DBLP]

  26. Process Variation Aware Issue Queue Design. [Citation Graph (, )][DBLP]

  27. Power management of variation aware chip multiprocessors. [Citation Graph (, )][DBLP]

  28. Selective shielding: a crosstalk-free bus encoding technique. [Citation Graph (, )][DBLP]

  29. Word-interleaved cache: an energy efficient data cache architecture. [Citation Graph (, )][DBLP]

  30. Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. [Citation Graph (, )][DBLP]

Search in 0.391secs, Finished in 0.392secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002