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Dhruva Acharyya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
    Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:33-40 [Conf]
  2. Dhruva Acharyya, Jim Plusquellic
    Impedance Profile of a Commercial Power Grid and Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:709-718 [Conf]
  3. Dhruva Acharyya, Jim Plusquellic
    Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:433-438 [Conf]
  4. Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel
    Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:278-293 [Journal]

  5. A physical unclonable function defined using power distribution system equivalent resistance variations. [Citation Graph (, )][DBLP]


  6. Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. [Citation Graph (, )][DBLP]


  7. Characterizing within-die variation from multiple supply port IDDQ measurements. [Citation Graph (, )][DBLP]


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