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Resve Saleh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Resve Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki
    DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:7-8 [Conf]
  2. Uthman Alsaiari, Resve Saleh
    Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:703-710 [Conf]
  3. Peter Hallschmid, Resve Saleh
    Fast Configuration of an Energy-Efficient Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:289-294 [Conf]
  4. Victor Aken Ova, Resve Saleh
    A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:103-108 [Conf]
  5. Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov
    Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:149-160 [Journal]
  6. Peter Hallschmid, Resve Saleh
    Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:732-737 [Conf]
  7. Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh
    Essential Fault-Tolerance Metrics for NoC Infrastructures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:37-42 [Conf]
  8. Amit Kedia, Resve Saleh
    Power Reduction of On-Chip Serial Links. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:865-868 [Conf]
  9. Xiongfei Meng, Karim Arabi, Resve Saleh
    A Novel Active Decoupling Capacitor Design in 90nm CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:657-660 [Conf]
  10. Uthman Alsaiari, Resve Saleh
    Testable and self-repairable structured logic design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  11. Delay macromodeling and estimation for RTL. [Citation Graph (, )][DBLP]


  12. PVT variation impact on voltage island formation in MPSoC design. [Citation Graph (, )][DBLP]


  13. Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. [Citation Graph (, )][DBLP]


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