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Asha Balijepalli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton
    Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:133-138 [Conf]
  2. Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
    Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:823-828 [Conf]

  3. Compact modeling of carbon nanotube transistor for early stage process-design exploration. [Citation Graph (, )][DBLP]


  4. A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. [Citation Graph (, )][DBLP]


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