|
Search the dblp DataBase
Zhiyi Yu:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Zhiyi Yu, Bevan M. Baas
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP] ISVLSI, 2006, pp:378-383 [Conf]
- Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung
AsAP: A Fine-Grained Many-Core Platform for DSP Applications. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2007, v:27, n:2, pp:34-45 [Journal]
- Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1125-1134 [Journal]
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. [Citation Graph (, )][DBLP]
A low-area interconnect architecture for chip multiprocessors. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.002secs
|