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Bevan M. Baas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhiyi Yu, Bevan M. Baas
    Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:378-383 [Conf]
  2. Bevan M. Baas, Zhiyi Yu, Michael J. Meeuwsen, Omar Sattari, Ryan W. Apperson, Eric Work, Jeremy Webb, Michael Lai, Tinoosh Mohsenin, Dean Truong, Jason Cheung
    AsAP: A Fine-Grained Many-Core Platform for DSP Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:2, pp:34-45 [Journal]
  3. Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen, Tinoosh Mohsenin, Bevan M. Baas
    A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1125-1134 [Journal]

  4. Circuit modeling for practical many-core architecture design exploration. [Citation Graph (, )][DBLP]


  5. An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes. [Citation Graph (, )][DBLP]


  6. Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. [Citation Graph (, )][DBLP]


  7. Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. [Citation Graph (, )][DBLP]


  8. A low-area interconnect architecture for chip multiprocessors. [Citation Graph (, )][DBLP]


  9. Dynamic voltage and frequency scaling circuits with two supply voltages. [Citation Graph (, )][DBLP]


  10. A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. [Citation Graph (, )][DBLP]


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