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Publications of Author

1. Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan
   Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:12-17 [Conf]
   
2. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
   A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2004, pp:585-592 [Conf]
   
3. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
   Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systems. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:314-317 [Conf]
   
4. Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
   A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:751-756 [Conf]
   
5. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
   Area and Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless System. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:734-737 [Conf]
   
6. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
   Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:744-749 [Conf]
   
7. Zahid Khan, Tughrul Arslan
   Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:349-354 [Conf]
   
8. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
   A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:1569-1574 [Conf]
   
9. Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan
   Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1281-1286 [Journal]
   
10. 
    Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture. [Citation Graph (, )][DBLP]