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Publications of Author

1. Nainesh Agarwal, Nikitas J. Dimopoulos
   DSPstone Benchmark of CoDeL's Automated Clock Gating Platform. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:508-509 [Conf]
   
2. Nainesh Agarwal, Nikitas J. Dimopoulos
   Using CoDeL to Rapidly Prototype Network Processsor Extensions. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2004, pp:333-342 [Conf]
   
3. Nainesh Agarwal, Nikitas J. Dimopoulos
   Efficient Automated Clock Gating Using CoDeL. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2006, pp:79-88 [Conf]
   
4. Nainesh Agarwal, Nikitas J. Dimopoulos
   Towards Automated Power Gating of Registers using CoDeL. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1629-1632 [Conf]
   
5. Nainesh Agarwal, Nikitas J. Dimopoulos
   Power efficient rapid hardware development using CoDel and automated clock gating. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
6. Nainesh Agarwal, Nikitas J. Dimopoulos
   Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2007, pp:294-303 [Conf]
   
7. 
   FSMD partitioning for low power using simulated annealing. [Citation Graph (, )][DBLP]
   
   
8. 
   FSMD Partitioning for Low Power Using ILP. [Citation Graph (, )][DBLP]
   
   
9. 
   Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. [Citation Graph (, )][DBLP]