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William H. McAnney: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paul H. Bardell, William H. McAnney
    Self-Testing of Multichip Logic Modules. [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:200-204 [Conf]
  2. Paul H. Bardell, William H. McAnney
    Parallel Pseudorandom Sequences for Built-In Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:302-308 [Conf]
  3. Paul H. Bardell, William H. McAnney
    Self-Test of Random Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:352-355 [Conf]
  4. William H. McAnney, Paul H. Bardell, V. P. Gupta
    Random Testing for Stuck-At Storage Cells in an Embedded Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:157-166 [Conf]
  5. William H. McAnney, Jacob Savir
    Built-In Checking of the Correct Self-Test Signature. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:54-59 [Conf]
  6. Jacob Savir, William H. McAnney
    Random Pattern Testability of Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:263-273 [Conf]
  7. Jacob Savir, William H. McAnney
    Identification of Failing Tests with Cycling Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:322-328 [Conf]
  8. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:100-105 [Conf]
  9. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:106-114 [Conf]
  10. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Testing for Coupled Cells in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:439-451 [Conf]
  11. Paul H. Bardell, William H. McAnney
    Pseudorandom Arrays for Built-In Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:7, pp:653-658 [Journal]
  12. William H. McAnney, Jacob Savir
    Built-In Checking of the Correct Self-Test Signature. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:9, pp:1142-1145 [Journal]
  13. Jacob Savir, William H. McAnney
    Random Pattern Testability of Delay Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:3, pp:291-300 [Journal]
  14. Jacob Savir, William H. McAnney
    A Multiple Seed Linear Feedback Shift Register. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:250-252 [Journal]
  15. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Fault Propagation Through Embedded Multiport Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:5, pp:592-602 [Journal]
  16. Jacob Savir, William H. McAnney, Salvatore R. Vecchio
    Testing for Coupled Cells in Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:10, pp:1177-1180 [Journal]

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