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Xinli Gu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xinli Gu, Sung Soo Chung, Frank Tsang, Jan Arild Tofte, Hamid Rahmanian
    An effort-minimized logic BIST implementation method. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1002-1010 [Conf]
  2. Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
    An Efficient and Economic Partitioning Approach for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:403-412 [Conf]
  3. Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
    Realizing High Test Quality Goals with Smart Test Resource Usage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:525-533 [Conf]
  4. Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung
    Re-Using DFT Logic for Functional and Silicon Debugging Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:648-656 [Conf]
  5. Mokhtar Hirech, James Beausang, Xinli Gu
    A new approach to scan chain reordering using physical design information. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:348-0 [Conf]
  6. Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung
    At-Speed Interconnect Test and Diagnosis of External Memories on a System. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:156-162 [Conf]
  7. Xinli Gu
    RT level testability-driven partitioning. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:176-183 [Conf]

  8. A controller testability analysis and enhancement technique. [Citation Graph (, )][DBLP]


  9. Testability analysis and improvement from VHDL behavioral specifications. [Citation Graph (, )][DBLP]


  10. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. [Citation Graph (, )][DBLP]


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