Search the dblp DataBase

Publications of Author

1. Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell
   Test Generation and Design for Test for a Large Multiprocessing DSP. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:149-156 [Conf]
   
2. Theo J. Powell, Dan Cline, Francis Hii
   A 256Meg SDRAM BIST for Disturb Test Application. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:200-208 [Conf]
   
3. Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
   BIST for Deep Submicron ASIC Memories with High Performance Application. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:386-392 [Conf]
   
4. Theo J. Powell, Fred Hwang, Bill Johnson
   Testability Features in the TMS370 Family of Microcomputers. [Citation Graph (0, 0)][DBLP]
   ITC, 1988, pp:153-160 [Conf]
   
5. Theo J. Powell, James R. Pair, Bernard G. Carbajal III
   Correlating Defects to Functional and I_DDQ Tests. [Citation Graph (0, 0)][DBLP]
   ITC, 1996, pp:501-510 [Conf]
   
6. Thirumalai Sridhar, D. S. Ho, Theo J. Powell, Satish M. Thatte
   Analysis and Simulation of Parallel Signature Analyzers. [Citation Graph (0, 0)][DBLP]
   ITC, 1982, pp:656-661 [Conf]
   
7. Satish M. Thatte, D. S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell
   An Architecture for Testable VLSI Processors. [Citation Graph (0, 0)][DBLP]
   ITC, 1982, pp:484-493 [Conf]
   
8. Aman Kokrady, Theo J. Powell, S. Ramakrishnan
   Reducing Design Verification Cycle Time through Testbench Redundancy. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:243-248 [Conf]
   
9. Theo J. Powell
   Consistently dominant fault model for tristate buffer nets. [Citation Graph (0, 0)][DBLP]
   VTS, 1996, pp:400-404 [Conf]
   
10. Theo J. Powell, James R. Pair, Melissa St. John, Doug Counce
    Delta Iddq for Testing Reliability. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:439-443 [Conf]