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Kwang-Ting (Tim) Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng
    BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1138-1147 [Conf]
  2. Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
    Testing High Speed VLSI Devices Using Slower Testers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:16-21 [Conf]
  3. Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng
    Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:204-209 [Conf]
  4. Chee-Kian Ong, Kwang-Ting (Tim) Cheng
    Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:123-128 [Conf]
  5. Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
    Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:237-246 [Conf]
  6. Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang
    Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:6-7 [Journal]
  7. Kwang-Ting (Tim) Cheng
    Dealing with early life failures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:85- [Journal]
  8. Kwang-Ting (Tim) Cheng
    The Need for a SiP Design and Test Infrastructure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:181- [Journal]
  9. Kwang-Ting (Tim) Cheng
    Vision from the Top. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:261- [Journal]
  10. Kwang-Ting (Tim) Cheng
    The New World of ESL Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:333- [Journal]
  11. Kwang-Ting (Tim) Cheng
    Single-Clock Partial Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:24-31 [Journal]
  12. Wayne Wei-Ming Dai, Kwang-Ting (Tim) Cheng
    Guest Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:4, pp:7-0 [Journal]
  13. Jing-Yang Jou, Kwang-Ting (Tim) Cheng
    Timing-Driven Partial Scan. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:4, pp:52-59 [Journal]
  14. Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
    Functionally Testable Path Delay Faults on a Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:6-14 [Journal]
  15. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
    New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:241-247 [Journal]
  16. Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
    Test Consideration for Nanometer-Scale CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:128-136 [Journal]
  17. Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
    A Signal Correlation Guided Circuit-SAT Solver. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2004, v:10, n:12, pp:1629-1654 [Journal]
  18. Mitchell Lin, Kwang-Ting (Tim) Cheng
    Testable design for advanced serial-link transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:695-700 [Conf]

  19. SCEMIT: a systemc error and mutation injection tool. [Citation Graph (, )][DBLP]


  20. An error tolerance scheme for 3D CMOS imagers. [Citation Graph (, )][DBLP]


  21. Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links. [Citation Graph (, )][DBLP]


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