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Jeff Rearick: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick
    Frequency detection-based boundary-scan testing of AC coupled nets. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:46-53 [Conf]
  2. Peter C. Maxwell, Jeff Rearick
    Deception by design: fooling ourselves with gate-level models. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:921-929 [Conf]
  3. Peter C. Maxwell, Jeff Rearick
    Estimation of defect-free IDDQ in submicron circuits using switch level simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:882-889 [Conf]
  4. Jeff Rearick
    Too much delay fault coverage is a bad thing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:624-633 [Conf]
  5. Jeff Rearick
    The Case of Partial Scan. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1032- [Conf]
  6. Jeff Rearick
    Buying time for the stuck-at fault model. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1167- [Conf]
  7. Jeff Rearick
    Practical scan test generation and application for embedded FIFOs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:294-300 [Conf]
  8. Jeff Rearick, Janak H. Patel
    Fast and Accurate CMOS Bridging Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:54-62 [Conf]
  9. Jeff Rearick, Sylvia Patterson, Krista Dorner
    Integrating Boundary Scan into Multi-GHz I/O Circuitry. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:560-566 [Conf]
  10. Suzette Vandivier, Mark Wahl, Jeff Rearick
    First IC Validation of IEEE Std. 1149.6. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:632-639 [Conf]
  11. Manish Sharma, Janak H. Patel, Jeff Rearick
    Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:15-21 [Conf]

  12. Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. [Citation Graph (, )][DBLP]


  13. Overview of Debug Standardization Activities. [Citation Graph (, )][DBLP]


  14. Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. [Citation Graph (, )][DBLP]


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