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Salvador Manich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, M. Santos
    Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:110-113 [Conf]
  2. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  3. Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez
    Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:80-89 [Conf]
  4. Salvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
    BIST Technique by Equally Spaced Test Vector Sequences. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:206-216 [Conf]
  5. Salvador Manich, Michael Nicolaidis, Joan Figueras
    Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:124-129 [Conf]
  6. Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
    Fault-Secure Parity Prediction Arithmetic Operators. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:60-71 [Journal]

  7. Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. [Citation Graph (, )][DBLP]


  8. Design and implementation of Automatic Test Equipment IP module. [Citation Graph (, )][DBLP]


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