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Sitaran Yadavalli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sitaran Yadavalli, Sudhakar M. Reddy
    SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:606-615 [Conf]
  2. Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy
    MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:110-115 [Conf]

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