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Ryusuke Egawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura
    A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2004, pp:572-578 [Conf]
  2. Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura
    Scaling Up Of Wave Pipelines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:439-445 [Conf]

  3. A Utility-Based Double Auction Mechanism for Efficient Grid Resource Allocation. [Citation Graph (, )][DBLP]


  4. Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture. [Citation Graph (, )][DBLP]


  5. Performance evaluation of NEC SX-9 using real science and engineering applications. [Citation Graph (, )][DBLP]


  6. Evaluation of fine grain 3-D integrated arithmetic units. [Citation Graph (, )][DBLP]


  7. 3D on-chip memory for the vector architecture. [Citation Graph (, )][DBLP]


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