The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

David Safránek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Safránek
    Visual Specification of Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ASE, 2003, pp:369-372 [Conf]
  2. David Safránek, Jirí Simsa
    VCD: A Visual Formalism for Specification of Heterogeneous Software Architectures. [Citation Graph (0, 0)][DBLP]
    SOFSEM, 2005, pp:320-329 [Conf]
  3. David Safránek
    SGCCS: A Graphical Language for Real-time Coordination. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:68, n:3, pp:- [Journal]
  4. Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák
    Verifying VHDL Designs with Multiple Clocks in SMV. [Citation Graph (0, 0)][DBLP]
    FMICS/PDMC, 2006, pp:148-164 [Conf]
  5. David Safránek
    Visual Specification of Systems with Heterogeneous Coordination Models. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:180, n:2, pp:107-121 [Journal]
  6. David Safránek
    Architectural Interoperability Checking in Visual Coordination Networks. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:181, n:, pp:81-96 [Journal]

  7. High-performance analysis of biological systems dynamics with the DiVinE model checker. [Citation Graph (, )][DBLP]


  8. BioDiVinE: A Framework for Parallel Analysis of Biological Models [Citation Graph (, )][DBLP]


  9. Parallel Model Checking Large-Scale Genetic Regulatory Networks with DiVinE. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002