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Yoshiyasu Ogasawara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yoshiyasu Ogasawara, Masashi Okamoto, Yukiko I. Nakano, Yong Xu, Toyoaki Nishida
    How to Make Robot a Robust and Interactive Communicator. [Citation Graph (0, 0)][DBLP]
    KES (3), 2005, pp:289-295 [Conf]
  2. Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
    A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:447-453 [Conf]
  3. Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
    Towards Reconfigurable Cache Memory for a Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:916-924 [Conf]
  4. Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
    A Model of Implementable SMT Processor on FPGA. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:909-915 [Conf]

  5. Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. [Citation Graph (, )][DBLP]

  6. An Effective Replacement Strategy of Cache Memory for an SMT Processor. [Citation Graph (, )][DBLP]

  7. Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. [Citation Graph (, )][DBLP]

  8. A two-layered approach to communicative artifacts. [Citation Graph (, )][DBLP]

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