|
Search the dblp DataBase
Michael Pellauer:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil
Synthesis of synchronous assertions with guarded atomic actions. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2005, pp:15-24 [Conf]
- Nirav Dave, Michael Pellauer, S. Gerding, Arvind
802.11a transmitter: a case study in microarchitectural exploration. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2006, pp:59-68 [Conf]
- Nirav Dave, Arvind, Michael Pellauer
Scheduling as Rule Composition. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2007, pp:51-60 [Conf]
- Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2007, pp:97-100 [Conf]
Soft connections: addressing the hardware-design modularity problem. [Citation Graph (, )][DBLP]
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. [Citation Graph (, )][DBLP]
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. [Citation Graph (, )][DBLP]
Search in 0.003secs, Finished in 0.003secs
|