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Publications of Author

1. Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
   Dataflow Predication. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:89-102 [Conf]
   
2. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
   Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:480-491 [Conf]
   
3. Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode
   Scaling to the End of Silicon with EDGE Architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Computer, 2004, v:37, n:7, pp:44-55 [Journal]
   
4. Taqi N. Buti, Robert G. McDonald, Zakaria Khwaja, Asit Ambekar, Hung Q. Le, William E. Burky, Bert Williams
   Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2005, v:49, n:1, pp:167-188 [Journal]
   
5. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
   TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
   TACO, 2004, v:1, n:1, pp:62-93 [Journal]
   
6. Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger
   Implementation and Evaluation of a Dynamically Routed Processor Operand Network. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:7-17 [Conf]
   
7. 
   Design and Implementation of the TRIPS Primary Memory System. [Citation Graph (, )][DBLP]
   
   
8. 
   Implementation and Evaluation of On-Chip Network Architectures. [Citation Graph (, )][DBLP]
   
   
9. 
   Critical path analysis of the TRIPS architecture. [Citation Graph (, )][DBLP]