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Tom Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John Pratt, Mahir Aydin, Tom Chen
    RC Extraction of Interconnects at Sub-Wavelength Dimensions. [Citation Graph (0, 0)][DBLP]
    Artificial Intelligence and Applications, 2005, pp:491-496 [Conf]
  2. Vinil Varghese, Tom Chen, Peter Young
    Stability analysis of active clock deskewing systems using a control theoretic approach. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:600-605 [Conf]
  3. Jinsang Kim, Tom Chen
    A VLSI Architecture for Image Sequence Segmentation using Edge Fusion. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:57-0 [Conf]
  4. Ajith Chandy, Tom Chen
    Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:984-985 [Conf]
  5. Tom Chen
    On the impact of on-chip inductance on signal nets under the influence of power grid noise. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:451-459 [Conf]
  6. Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
    High quality behavioral verification using statistical stopping criteria. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:411-419 [Conf]
  7. Jayashree Sridharan, Tom Chen
    Modeling multiple input switching of CMOS gates in DSM technology using HDMR. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:626-631 [Conf]
  8. Vinil Varghese, Tom Chen, Peter M. Young
    Systematic Analysis of Active Clock Deskewing Systems Using Control Theory. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:820-825 [Conf]
  9. Amjad Hajjar, Tom Chen
    An Accurate Coverage Forecasting Model for Behavioral Model Verification. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:104-110 [Conf]
  10. Gerald Esch Jr., Tom Chen
    Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:312-320 [Conf]
  11. Von-Kyoung Kim, Tom Chen
    Assessing Defect Coverage of Memory Testing Algorithms. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:340-0 [Conf]
  12. Von-Kyoung Kim, Tom Chen, Mick Tegethoff
    Fault Coverage Estimation for Early Stage of VLSI Design. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:105-108 [Conf]
  13. Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
    RUBASTEM: A Method for Testing VHDL Behavioral Models. [Citation Graph (0, 0)][DBLP]
    HASE, 2004, pp:187-196 [Conf]
  14. Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
    How Much Testing is Enough? Applying Stopping Rules to Behavioral Model Testing. [Citation Graph (0, 0)][DBLP]
    HASE, 1999, pp:249-256 [Conf]
  15. Anneliese von Mayrhauser, Andre Bai, Tom Chen, Charles Anderson, Amjad Hajjar
    Fast Antirandom (FAR) Test Generation. [Citation Graph (0, 0)][DBLP]
    HASE, 1998, pp:262-269 [Conf]
  16. Fahad M. Alzahrani, Tom Chen
    On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:132-137 [Conf]
  17. Tom Chen, Glen Sunada
    An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:576-581 [Conf]
  18. Geun Rae Cho, Tom Chen
    On The Impact of Technology Scaling On Mixed PTL/Static Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:322-326 [Conf]
  19. Glen Sunada, Jain Jin, Matt Berzins, Tom Chen
    COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:546-550 [Conf]
  20. Chien-Chih Chen, Tom Chen
    Modified Rate-Distortion Function with Optimal Classification for Wavelet Coding. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1997, pp:86-89 [Conf]
  21. Tom Chen, Li Zhu
    A Fast 1024-Point FFT Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:646-647 [Conf]
  22. Jinsang Kim, Tom Chen
    Segmentation of Image Sequences Using SOFM Networks. [Citation Graph (0, 0)][DBLP]
    ICPR, 2000, pp:3877-3880 [Conf]
  23. Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar
    Efficient Verification of Behavioral Models Using Sequential Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:398-406 [Conf]
  24. Tom Chen
    Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:173-178 [Conf]
  25. Tom Chen, Amjad Hajjar
    Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:183-188 [Conf]
  26. Tom Chen, Anneliese von Mayrhauser, Amjad Hajjar, Charles Anderson, Mehmet Sahinoglu
    Achieving the Quality of Verification for Behavioral Models with Minimum Effort. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:234-0 [Conf]
  27. Geun Rae Cho, Tom Chen
    Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:458-463 [Conf]
  28. Geun Rae Cho, Tom Chen
    Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:55-60 [Conf]
  29. Amjad Hajjar, Tom Chen
    Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:304-309 [Conf]
  30. Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
    Stopping Criteria Comparison: Towards High Quality Behavioral Verification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:31-37 [Conf]
  31. Medha Kulkarni, Tom Chen
    A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:331-336 [Conf]
  32. Charles Thangaraj, Tom Chen
    Power andPerformance Analysis for Early Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:473-478 [Conf]
  33. Tom Chen, Glen Sunada
    A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:623-631 [Conf]
  34. Von-Kyoung Kim, Tom Chen, Mick Tegethoff
    ASIC Manufacturing Test Cost Prediction at Early Design Stage. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:356-361 [Conf]
  35. Von-Kyoung Kim, Mick Tegethoff, Tom Chen
    ASIC Yield Estimation at Early Design Cycle. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:590-594 [Conf]
  36. Mick Tegethoff, Tom Chen
    Defects, Fault Coverage, Yield and Cost in Board Manufacturing. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:539-547 [Conf]
  37. Mick Tegethoff, Tom Chen
    Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:903-910 [Conf]
  38. Geun Rae Cho, Tom Chen
    On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:289-294 [Conf]
  39. Charles Anderson, Anneliese von Mayrhauser, Tom Chen
    Assessing Neural Networks as Guides for Testing Activities. [Citation Graph (0, 0)][DBLP]
    IEEE METRICS, 1996, pp:155-165 [Conf]
  40. Jingsang Kim, Tom Chen
    Real-time Video Objects Segmentation using a Highly Pipelined Microarchitecture. [Citation Graph (0, 0)][DBLP]
    VIIP, 2001, pp:483-488 [Conf]
  41. Anneliese Amschler Andrews, Andrew O'Fallon, Tom Chen
    A Rule-Based Software Testing Method for VHDL Models. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:92-0 [Conf]
  42. Geun Rae Cho, Tom Chen
    On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:513-0 [Conf]
  43. Jayashree Sridharan, Tom Chen
    Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:323-328 [Conf]
  44. Mick Tegethoff, Tom Chen
    Sensitivity Analysis of Critical Parameters in Board Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:1, pp:58-63 [Journal]
  45. Amjad Hajjar, Tom Chen
    VLSI Architecture for Real-Time Edge Linking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1999, v:21, n:1, pp:89-94 [Journal]
  46. Jinsang Kim, Tom Chen
    Multiple feature clustering for image sequence segmentation. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition Letters, 2001, v:22, n:11, pp:1207-1217 [Journal]
  47. Fahad M. Alzahrani, Tom Chen
    A Real-Time Edge Detector: Algorithm and VLSI Architecture. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1997, v:3, n:5, pp:363-378 [Journal]
  48. Tom Chen, Amjad Hajjar
    Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1677-1683 [Journal]
  49. Geun Rae Cho, Tom Chen
    Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:229-242 [Journal]
  50. Von-Kyoung Kim, Tom Chen
    On comparing functional fault coverage and defect coverage for memory testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1676-1683 [Journal]
  51. Medha Kulkarni, Tom Chen
    A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1336-1346 [Journal]
  52. Jinsang Kim, Tom Chen
    A VLSI architecture for video-object segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:1, pp:83-96 [Journal]
  53. Gerald Esch Jr., Tom Chen
    Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1253-1257 [Journal]
  54. Daniela De Venuto, Tom Chen
    International Symposium on Quality Electronic Design. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:787-788 [Journal]
  55. Tom Chen, Glen Sunada
    Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:88-97 [Journal]
  56. Tom Chen, Glen Sunada, Jain Jin
    COBRA: a 100-MOPS single-chip programmable and expandable FFT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:174-182 [Journal]

  57. Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. [Citation Graph (, )][DBLP]


  58. Design target exploration for meeting time-to-market using pareto analysis. [Citation Graph (, )][DBLP]


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