Ajith Chandy, Tom Chen Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:984-985 [Conf]
Tom Chen On the impact of on-chip inductance on signal nets under the influence of power grid noise. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:451-459 [Conf]
Gerald Esch Jr., Tom Chen Design of CMOS IO Drivers with Less Sensitivity to Process, Voltage, and Temperature Variations. [Citation Graph (0, 0)][DBLP] DELTA, 2004, pp:312-320 [Conf]
Amjad Hajjar, Tom Chen Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian Criteria. [Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:304-309 [Conf]
Medha Kulkarni, Tom Chen A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects. [Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:331-336 [Conf]
Geun Rae Cho, Tom Chen On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. [Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:289-294 [Conf]
Geun Rae Cho, Tom Chen On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:513-0 [Conf]
Tom Chen, Amjad Hajjar Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1677-1683 [Journal]
Geun Rae Cho, Tom Chen Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:229-242 [Journal]
Von-Kyoung Kim, Tom Chen On comparing functional fault coverage and defect coverage for memory testing. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1676-1683 [Journal]
Medha Kulkarni, Tom Chen A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1336-1346 [Journal]
Jinsang Kim, Tom Chen A VLSI architecture for video-object segmentation. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:1, pp:83-96 [Journal]
Gerald Esch Jr., Tom Chen Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1253-1257 [Journal]