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Sakir Sezer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Motasem Abdelghani, Sakir Sezer, Emi Garcia, Mu Jun
    Packet Classification Using Adaptive Rules Cutting (ARC). [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:28-33 [Conf]
  2. Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John McCanny
    Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. [Citation Graph (0, 0)][DBLP]
    AICT/ICIW, 2006, pp:56- [Conf]
  3. Kieran McLaughlin, Stephen O'Kane, Sakir Sezer
    Implementing High Speed IP Address Lookups in Hardware. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:140-144 [Conf]
  4. Kieran McLaughlin, Niall O'Connor, Sakir Sezer
    Exploring CAM Design For Network Processing Using FPGA Technology. [Citation Graph (0, 0)][DBLP]
    AICT/ICIW, 2006, pp:84- [Conf]
  5. P. Moore, Máire McLoone, Sakir Sezer
    Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:296-299 [Conf]
  6. Stephen O'Kane, Colm McKillen, Sakir Sezer
    The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:352-356 [Conf]
  7. Stephen O'Kane, Sakir Sezer, Lum Soong Lit
    A Study of Shared Buffer Memory Segmentation for Packet Switched Networks. [Citation Graph (0, 0)][DBLP]
    AICT/ICIW, 2006, pp:55- [Conf]
  8. Ciaran Toal, Sakir Sezer
    A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:357-362 [Conf]
  9. Steven Walsh, Emi Garcia, Sakir Sezer
    Assessing the Impact of Rainfall on System Bandwidth for Broadband Fixed Wireless Applications. [Citation Graph (0, 0)][DBLP]
    AICT/SAPIR/ELETE, 2005, pp:279-283 [Conf]
  10. Ciaran Toal, Sakir Sezer, Xing Yu
    A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:271-272 [Conf]
  11. Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron
    A Virtual Hardware Handler for RTR Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:262-263 [Conf]
  12. Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall
    Fast Partial Reconfiguration for FCCMs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:318-319 [Conf]
  13. Brendan McAllister, Sakir Sezer, Ciaran Toal
    Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1149-1152 [Conf]
  14. Stephen Dawson, Sakir Sezer
    A Framework for Remote EDA Tooling and Distributed Resource Management. [Citation Graph (0, 0)][DBLP]
    International Conference on Internet Computing, 2003, pp:213-218 [Conf]
  15. Stephen Dawson, Sakir Sezer
    Web Based Service Provision - A Case Study: Electronic Design Automation. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:1057-1066 [Conf]
  16. Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson
    Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:876-884 [Conf]
  17. V. Stewart, C. F. N. Cowan, Sakir Sezer
    Adaptive Echo Cancellation for Packet-Based Networks. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:516-525 [Conf]
  18. Ciaran Toal, Sakir Sezer
    The Implementation of Scalable ATM Frame Delineation Circuits. [Citation Graph (0, 0)][DBLP]
    ICT, 2004, pp:1047-1056 [Conf]
  19. Alan Marshall, Sakir Sezer
    The Influence of Cumulative Switch Delay in Multiple Service Class Networks. [Citation Graph (0, 0)][DBLP]
    IMSA, 1999, pp:409-414 [Conf]
  20. Sakir Sezer, Ciaran Toal, Emi Garcia, V. Stewart
    A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  21. Ciaran Toal, Sakir Sezer
    A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:179- [Conf]
  22. Ciaran Toal, Sakir Sezer
    Investigation into programmability for layer 2 protocol frame delineation architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  23. Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John McCanny
    Design and analysis of matching circuit architectures for a closest match lookup. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  24. Ciaran Toal, Sakir Sezer
    A 32-Bit SoPC Implementation of a P5. [Citation Graph (0, 0)][DBLP]
    ISCC, 2003, pp:504-507 [Conf]
  25. Colm McKillen, Sakir Sezer, Xin Yang
    High performance service-time-stamp computation for WFQ IP packet scheduling. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:65-70 [Conf]
  26. Ciaran Toal, Sakir Sezer, Xin Yang
    A VLSI GFP Frame Delineation Circuit. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:454-455 [Conf]
  27. Alan Marshall, Emi Garcia-Palacios, Sakir Sezer, David Chieng
    Performance Analysis of Access Points In Cellular Wireless ATM Networks. [Citation Graph (0, 0)][DBLP]
    MMNS, 2000, pp:31-44 [Conf]

  28. Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. [Citation Graph (, )][DBLP]

  29. An FPGA Based Memory Efficient Shared Buffer Implementation. [Citation Graph (, )][DBLP]

  30. Systolic Array Based Architecture for Variable Block-Size Motion Estimation. [Citation Graph (, )][DBLP]

  31. An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. [Citation Graph (, )][DBLP]

  32. Novel Content Addressable Memory Architecture for Adaptive Systems. [Citation Graph (, )][DBLP]

  33. High-Speed IP Address Lookups Using Hardware Based Tree Structures. [Citation Graph (, )][DBLP]

  34. FPGA-Based Lookup Circuit for Session-Based IP Packet Classification. [Citation Graph (, )][DBLP]

  35. Classification of P2P and HTTP Using Specific Protocol Characteristics. [Citation Graph (, )][DBLP]

  36. High performance IP lookup circuit using DDR SDRAM. [Citation Graph (, )][DBLP]

  37. Multi-standard sub-pixel interpolation architecture for video Motion Estimation. [Citation Graph (, )][DBLP]

  38. Application development flow for on-chip distributed architectures. [Citation Graph (, )][DBLP]

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