An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication. [Citation Graph (, )][DBLP]
Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA. [Citation Graph (, )][DBLP]
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach. [Citation Graph (, )][DBLP]
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA. [Citation Graph (, )][DBLP]
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