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Yuanlin Lu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yuanlin Lu, Vishwani D. Agrawal
    Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:217-226 [Conf]
  2. Yuanlin Lu, Vishwani D. Agrawal
    Statistical Leakage and Timing Optimization for Submicron Process Variation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:439-444 [Conf]
  3. Yuanlin Lu, Vishwani D. Agrawal
    CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:378-387 [Journal]

  4. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. [Citation Graph (, )][DBLP]

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