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David Guerrero Martos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, J. Viejo
    Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:337-347 [Conf]
  2. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, J. Viejo
    Logic-Level Fast Current Simulation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:425-435 [Conf]

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