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Pilar Parra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta
    Optimization of Master-Slave Flip-Flops for High-Performance Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:439-449 [Conf]
  2. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:209-218 [Conf]
  3. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:491-500 [Conf]
  4. Pilar Parra, Antonio J. Acosta, Manuel Valencia
    Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:448-457 [Conf]
  5. Javier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta
    Asymmetric clock driver for improved power and noise performances. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:893-896 [Conf]
  6. Pilar Parra, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia
    Selective Clock-Gating for Low-Power Synchronous Counters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:11-19 [Journal]

  7. Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. [Citation Graph (, )][DBLP]


  8. EDROOM, Herramienta Libre de Modelado y Generación Automática de Código para Sistemas de Tiempo Real. [Citation Graph (, )][DBLP]


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