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Alin Razafindraibe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:634-644 [Conf]
  2. Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
    A Method to Design Compact Dual-rail Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:571-580 [Conf]
  3. Alin Razafindraibe, Philippe Maurine
    A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:394-403 [Conf]
  4. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:340-351 [Conf]
  5. Philippe Hoogvorst, Sylvain Guilley, Sumanta Chau, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
    A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:15-22 [Conf]
  6. Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
    Security evaluation of dual rail logic against DPA attacks. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:181-186 [Conf]
  7. Alin Razafindraibe, Michel Robert, Philippe Maurine
    Compact and Secured Primitives for the Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:20-26 [Journal]

  8. Improvement of dual rail logic as a countermeasure against DPA. [Citation Graph (, )][DBLP]

  9. Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]

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