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Mitaro Namiki: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
    Implementation of PC Cluster System with Memory Mapped File by Commodity OS. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:902-908 [Conf]
  2. Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
    Dynamic Allocation of Physical Register Banks for an SMT Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:317-323 [Conf]
  3. Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
    Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1775-1781 [Conf]
  4. Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
    A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:447-453 [Conf]
  5. Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
    Towards Reconfigurable Cache Memory for a Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:916-924 [Conf]
  6. Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
    Implementation and Evaluation of a Thread Library for Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:609-615 [Conf]
  7. Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
    A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1669-1675 [Conf]
  8. Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
    A Model of Implementable SMT Processor on FPGA. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:909-915 [Conf]
  9. Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
    Development of a Thread Scheduler for SMT Processor Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:454-460 [Conf]

  10. Proposal of a multi-core processor architecture for effective evolutionary computation. [Citation Graph (, )][DBLP]


  11. A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]


  12. Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. [Citation Graph (, )][DBLP]


  13. Adaptive power gating for function units in a microprocessor. [Citation Graph (, )][DBLP]


  14. Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX". [Citation Graph (, )][DBLP]


  15. A CS unplugged design pattern. [Citation Graph (, )][DBLP]


  16. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]


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