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Publications of Author

1. Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
   Dynamic Allocation of Physical Register Banks for an SMT Processor. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2004, pp:317-323 [Conf]
   
2. Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
   Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2003, pp:1775-1781 [Conf]
   
3. Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
   A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2005, pp:447-453 [Conf]
   
4. Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
   Implementation and Evaluation of a Thread Library for Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2003, pp:609-615 [Conf]
   
5. Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
   A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2003, pp:1669-1675 [Conf]
   
6. Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
   Development of a Thread Scheduler for SMT Processor Architecture. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2005, pp:454-460 [Conf]