Search the dblp DataBase

Publications of Author

1. Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
   Dynamic Allocation of Physical Register Banks for an SMT Processor. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2004, pp:317-323 [Conf]
   
2. Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
   A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2005, pp:447-453 [Conf]
   
3. Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
   Towards Reconfigurable Cache Memory for a Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2006, pp:916-924 [Conf]
   
4. Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
   A Model of Implementable SMT Processor on FPGA. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2006, pp:909-915 [Conf]
   
5. Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
   Development of a Thread Scheduler for SMT Processor Architecture. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2005, pp:454-460 [Conf]