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Wolfgang Stadler :
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Wolfgang Stadler Einführung verteilter Systeme in einem Unternehmen der Markenartikelindustrie - Organisatorische Konsequenzen. [Citation Graph (0, 0)][DBLP ] GI-Fachgespräch über Rechenzentren, 1993, pp:128-134 [Conf ] K. Esmark , Wolfgang Stadler , M. Wendel , Harald Gossner , X. Guggenmos , Wolfgang Fichtner Advanced 2D/3D ESD device simulation - a powerful tool already used in a pre-Si phase. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2001, v:41, n:11, pp:1761-1770 [Journal ] Wolfgang Stadler , K. Esmark , Harald Gossner , M. Streibl , M. Wendel , Wolfgang Fichtner , Dionyz Pogany , Martin Litzenberger , E. Gornik Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2002, v:42, n:9-11, pp:1267-1274 [Journal ] M. Streibl , K. Esmark , A. Sieck , Wolfgang Stadler , M. Wendel , J. Szatkowski , Harald Gossner Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2003, v:43, n:7, pp:1001-1010 [Journal ] Heinrich Wolf , Horst A. Gieser , Wolfgang Stadler , Wolfgang Wilkening Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:2, pp:279-285 [Journal ] S. Bargstädt-Franke , Wolfgang Stadler , K. Esmark , M. Streibl , K. Domanski , Horst A. Gieser , Heinrich Wolf , W. Bala Transient latch-up: experimental analysis and device simulation. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:2, pp:297-304 [Journal ] M. Streibl , F. Zängl , K. Esmark , R. Schwencker , Wolfgang Stadler , Harald Gossner , S. Drüen , D. Schmitt-Landsiedel High abstraction level permutational ESD concept analysis. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:2, pp:313-321 [Journal ] Wolfgang Stadler Guest editorial. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:2, pp:199-200 [Journal ] Wolfgang Stadler , K. Esmark , K. Reynders , M. Zubeidat , M. Graf , Wolfgang Wilkening , J. Willemen , N. Qu , S. Mettler , M. Etherton Test circuits for fast and reliable assessment of CDM robustness of I/O stages. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2005, v:45, n:2, pp:269-277 [Journal ] K. Domanski , B. Póltorak , S. Bargstädt-Franke , Wolfgang Stadler , W. Bala Physical fundamentals of external transient latch-up and corrective actions. [Citation Graph (0, 0)][DBLP ] Microelectronics Reliability, 2006, v:46, n:5-6, pp:689-701 [Journal ] Search in 0.003secs, Finished in 0.004secs