The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Holger Ruckdeschel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
    Automatic FIR Filter Generation for FPGAs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:51-61 [Conf]
  2. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
    Efficient control generation for mapping nested loop programs onto processor arrays. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:5-6, pp:300-309 [Journal]

  3. A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. [Citation Graph (, )][DBLP]


  4. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002