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Publications of Author

1. Houman Homayoun, Amirali Baniasadi
   Reducing Execution Unit Leakage Power in Embedded Processors. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2006, pp:299-308 [Conf]
   
2. Houman Homayoun, Ted H. Szymanski
   Reducing the Instruction Queue Leakage Power in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
   CCECE, 2006, pp:1685-1689 [Conf]
   
3. 
   Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. [Citation Graph (, )][DBLP]
   
   
4. 
   A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). [Citation Graph (, )][DBLP]
   
   
5. 
   Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. [Citation Graph (, )][DBLP]
   
   
6. 
   Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. [Citation Graph (, )][DBLP]
   
   
7. 
   Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. [Citation Graph (, )][DBLP]
   
   
8. 
   RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. [Citation Graph (, )][DBLP]
   
   
9. 
   Reducing leakage power in peripheral circuits of L2 caches. [Citation Graph (, )][DBLP]
   
   
10. 
    ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. [Citation Graph (, )][DBLP]
    
    
11. 
    Adaptive techniques for leakage power management in L2 cache peripheral circuits. [Citation Graph (, )][DBLP]
    
    
12. 
    Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
13. 
    Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. [Citation Graph (, )][DBLP]
    
    
14. 
    Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. [Citation Graph (, )][DBLP]
    
    
15. 
    A centralized cache miss driven technique to improve processor power dissipation. [Citation Graph (, )][DBLP]