The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Takeshi Ikenaga: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takeshi Ikenaga, Kenji Kawahara, Tetsuya Takine, Yuji Oie
    Analysis of Delayed Reservation Scheme in Server-Based QoS Management Network. [Citation Graph (0, 0)][DBLP]
    AINA, 2003, pp:140-145 [Conf]
  2. Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto
    High-throughput decoder for low-density parity-check code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:112-113 [Conf]
  3. Lingfeng Li, Satoshi Goto, Takeshi Ikenaga
    An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:623-626 [Conf]
  4. Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
    Reconfigurable adaptive FEC system with interleaving. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1252-1255 [Conf]
  5. Takeshi Ikenaga, Takeshi Ogura
    CAM²: A Highly-Parallel 2D Cellular Automata Architecture for Real-Time and Palm-Top Pixel-Level Image Processing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:203-212 [Conf]
  6. Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto
    A VLSI array processing oriented fast fourier transform algorithm and hardware implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:291-295 [Conf]
  7. Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto
    A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:20-24 [Conf]
  8. Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga
    Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:160-163 [Conf]
  9. Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa
    Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:503-510 [Conf]
  10. Yangxing Liu, Satoshi Goto, Takeshi Ikenaga
    A Robust Algorithm for Text Detection in Color Images. [Citation Graph (0, 0)][DBLP]
    ICDAR, 2005, pp:399-405 [Conf]
  11. Takeshi Ikenaga, Takeshi Ogura
    Real-Time Morphology Processing Using Highly Parallel 2D Cellular Automata CAM2. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1997, pp:562-565 [Conf]
  12. Yangxing Liu, Satoshi Goto, Takeshi Ikenaga
    An accurate and low complexity approach of detecting circular shape objects in still color images. [Citation Graph (0, 0)][DBLP]
    ICIP (1), 2005, pp:333-336 [Conf]
  13. Manzoor Hashmani, Mikio Yoshida, Takeshi Ikenaga, Yuji Oie
    Management and Realization of SLA for Providing Network QoS. [Citation Graph (0, 0)][DBLP]
    ICN (1), 2001, pp:398-408 [Conf]
  14. Seiichiro Hiratsuka, Satoshi Goto, Takaaki Baba, Takeshi Ikenaga
    A locally adaptive subsampling algorithm for software based motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2891-2894 [Conf]
  15. Yoshiaki Ohta, Kenji Kawahara, Takeshi Ikenaga, Yuji Oie
    Performance Evaluation of Channel Switching Scheme for Packet Data Transmission in Radio Network Controller. [Citation Graph (0, 0)][DBLP]
    NETWORKING, 2002, pp:648-659 [Conf]
  16. Hiroyuki Koga, Takeshi Ikenaga, Yoshiaki Hori, Yuji Oie
    Out-of-Sequence in Packet Arrivals due to Layer 2 ARQ and Its Impact on TCP Performance in W-CDMA Networks. [Citation Graph (0, 0)][DBLP]
    SAINT, 2003, pp:398-401 [Conf]
  17. Hedia Kochkar, Takeshi Ikenaga, Kenji Kawahara, Yuji Oie
    Multi-class QoS routing strategies based on the network state. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2005, v:28, n:11, pp:1348-1355 [Journal]
  18. Takeshi Ikenaga, Takeshi Ogura
    CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:7, pp:788-801 [Journal]
  19. Takeshi Ikenaga, Takeshi Ogura
    Real-time morphology processing using highly parallel 2-D cellular automata CAM2. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Image Processing, 2000, v:9, n:12, pp:2018-2026 [Journal]
  20. Yutaka Fukuda, Hiroyuki Koga, Takeshi Ikenaga, Yuji Oie
    Performance evaluation of TCP under dynamic allocation scheme for down-link transmission rate in W-CDMA systems. [Citation Graph (0, 0)][DBLP]
    Wireless Communications and Mobile Computing, 2004, v:4, n:2, pp:223-232 [Journal]
  21. Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto
    Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3659-3662 [Conf]
  22. Changqi Yang, S. Goto, T. Ikenaga
    High performance VLSI architecture of fractional motion estimation in H.264 for HDTV. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  23. Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
    A parallel LSI architecture for LDPC decoder improving message-passing schedule. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  24. Seiichiro Hiratsuka, Satoshi Goto, Takeshi Ikenaga
    An ultra-low complexity motion estimation algorithm and its implementation of specific processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  25. Yangxing Liu, Takeshi Ikenaga, Satoshi Goto
    An MRF model-based approach to the detection of rectangular shape objects in color images. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2007, v:87, n:11, pp:2649-2658 [Journal]

  26. A Novel Approach of Rectangular Shape Object Detection in Color Images Based on An MRF Model. [Citation Graph (, )][DBLP]


  27. Geometric Primitives Detection in Aerial Image. [Citation Graph (, )][DBLP]


  28. A 7-Round Parallel Hardware-Saving Accelerator for Gaussian and DoG Pyramid Construction Part of SIFT. [Citation Graph (, )][DBLP]


  29. A high performance LDPC decoder for IEEE802.11n standard. [Citation Graph (, )][DBLP]


  30. A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm. [Citation Graph (, )][DBLP]


  31. Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. [Citation Graph (, )][DBLP]


  32. Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264. [Citation Graph (, )][DBLP]


  33. A motion vector difference based self-incremental adaptive search range algorithm for variable block size motion estimation. [Citation Graph (, )][DBLP]


  34. Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt. [Citation Graph (, )][DBLP]


  35. Macroblock feature and motion involved multi-stage fast inter mode decision algorithm in H.264/AVC video coding. [Citation Graph (, )][DBLP]


  36. Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC. [Citation Graph (, )][DBLP]


  37. VLSI Oriented Fast Multiple Reference Frame Motion Estimation Algorithm for H.264/AVC. [Citation Graph (, )][DBLP]


  38. Fast motion estimation for H.264/AVC using image edge features. [Citation Graph (, )][DBLP]


  39. Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC. [Citation Graph (, )][DBLP]


  40. Content aware configurable architecture for H.264/AVC integer motion estimation engine. [Citation Graph (, )][DBLP]


  41. VLSI friendly computation reduction scheme in H.264/AVC motion estimation. [Citation Graph (, )][DBLP]


  42. Power-efficient LDPC code decoder architecture. [Citation Graph (, )][DBLP]


  43. Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation. [Citation Graph (, )][DBLP]


  44. A Fast Hybrid Decision Algorithm for H.264/AVC Intra Prediction Based on Entropy Theory. [Citation Graph (, )][DBLP]


  45. Adaptively Adjusted Gaussian Mixture Models for Surveillance Applications. [Citation Graph (, )][DBLP]


  46. A New Video Encryption Scheme for H.264/AVC. [Citation Graph (, )][DBLP]


  47. Compressing Packets Adaptively Inside Networks. [Citation Graph (, )][DBLP]


  48. Streaming Media Caching on Advanced Relay Nodes. [Citation Graph (, )][DBLP]


  49. Development of Single Sign-On System with Hardware Token and Key Management Server. [Citation Graph (, )][DBLP]


  50. Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications. [Citation Graph (, )][DBLP]


  51. Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding. [Citation Graph (, )][DBLP]


  52. A New Multiscale Line Detection Approach for Aerial Image with Complex Scene. [Citation Graph (, )][DBLP]


  53. A Novel Hybrid Approach of Color Image Segmentation. [Citation Graph (, )][DBLP]


  54. A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile. [Citation Graph (, )][DBLP]


  55. Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over Internet. [Citation Graph (, )][DBLP]


  56. Memory-Efficient Accelerating Schedule for LDPC Decoder. [Citation Graph (, )][DBLP]


  57. Early detection algorithms for 8×8 all-zero blocks in H.264/AVC. [Citation Graph (, )][DBLP]


  58. H.264/AVC Fractional Motion Estimation Engine with Computation Reusing in HDTV1080P Real-Time Encoding Applications. [Citation Graph (, )][DBLP]


  59. 32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application. [Citation Graph (, )][DBLP]


  60. An Adaptive Spatial Error Concealment for H.264/AVC Video Stream. [Citation Graph (, )][DBLP]


  61. A Macroblock-Level Rate Control Algorithm for H.264/AVC Video Coding with Context-Adaptive MAD Prediction Model. [Citation Graph (, )][DBLP]


  62. Motion Detection Based on Background Modeling and Performance Analysis for Outdoor Surveillance. [Citation Graph (, )][DBLP]


  63. A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT. [Citation Graph (, )][DBLP]


  64. A Foreground Extraction Algorithm Based on Adaptively Adjusted Gaussian Mixture Models. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.308secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002