The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sao-Jie Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chin-Fu Ku, Sao-Jie Chen, Jan-Ming Ho, Ray-I Chang
    Improving End-to-End Performance by Active Queue Management. [Citation Graph (0, 0)][DBLP]
    AINA, 2005, pp:337-340 [Conf]
  2. Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen
    Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. [Citation Graph (0, 0)][DBLP]
    APSEC, 2001, pp:71-78 [Conf]
  3. Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
    An Automatic Router for the Pin Grid Array Package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:133-136 [Conf]
  4. Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho
    An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:69-72 [Conf]
  5. Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen
    Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:60-65 [Conf]
  6. Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen
    Multilevel full-chip routing for the X-based architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:597-602 [Conf]
  7. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
    A Fast Crosstalk- and Performance-Driven Multilevel Routing System. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:382-387 [Conf]
  8. Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
    An Even Wiring Approach to the Ball Grid Array Package Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:303-306 [Conf]
  9. Jih-Ming Fu, Win-Bin See, Pao-Ann Hsiung, Jen-Ming Chao, Sao-Jie Chen
    A Java-Based Distributed System Framework for Real-Time Development. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshop on Distributed Real-Time Systems, 2000, pp:0-0 [Conf]
  10. Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
    TCN: Scalable Hierarchical Hypercubes. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2002, pp:11-16 [Conf]
  11. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    A crosstalk aware two-pin net router. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:485-488 [Conf]
  12. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    Minimizing coupling jitter by buffer resizing for coupled clock networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:509-512 [Conf]
  13. Fong-Ming Shyu, Sao-Jie Chen
    A distributed and object-oriented framework for VLSI physical design automation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:77-80 [Conf]
  14. Chu Yu, Sao-Jie Chen
    Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 1999, pp:524-527 [Conf]
  15. Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen
    VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Symposium on Object-Oriented Real-Time Distributed Computing, 2002, pp:322-329 [Conf]
  16. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
    Multilevel routing with antenna avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:34-40 [Conf]
  17. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    Minimizing Inter-Clock Coupling Jitter. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:333-338 [Conf]
  18. Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
    A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:2982-2987 [Conf]
  19. Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
    Software Platform for Embedded Software Development. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2003, pp:545-557 [Conf]
  20. Jong-Sheng Cherng, Sao-Jie Chen
    An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:70-0 [Conf]
  21. Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
    Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TOOLS (24), 1997, pp:284-293 [Conf]
  22. Yaw-Jen Lin, Mei-Ju Su, Sao-Jie Chen, Suh-Chin Wang, Chiu-I Lin, Heng-Shuen Chen
    A Study of Ubiquitous Monitor with RFID in an Elderly Nursing Home. [Citation Graph (0, 0)][DBLP]
    MUE, 2007, pp:336-340 [Conf]
  23. Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
    Generalized terminal connectivity problem for multilayer layout scheme. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1990, v:22, n:7, pp:423-433 [Journal]
  24. Jiann-Fu Lin, Sao-Jie Chen
    Performance Bounds on Scheduling Parallel Tasks with Setup Time on Hypercube Systems. [Citation Graph (0, 0)][DBLP]
    Informatica (Slovenia), 1995, v:19, n:3, pp:- [Journal]
  25. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
    Multilevel routing with jumper insertion for antenna avoidance. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:420-432 [Journal]
  26. Chia-Chun Tsai, Sao-Jie Chen
    A Linear Time Algorithm for Planar Moat Routing. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1994, v:10, n:1, pp:111-127 [Journal]
  27. Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
    An H-V Tile-Expansion Router. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1990, v:6, n:3, pp:173-189 [Journal]
  28. Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan
    A Three-Stage One-Sided Rearrangeable Polygonal Switching Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1291-1294 [Journal]
  29. Yu Hen Hu, Sao-Jie Chen
    GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:836-845 [Journal]
  30. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
    Fast postplacement optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:102-118 [Journal]
  31. Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee
    Crosstalk- and performance-driven multilevel full-chip routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:869-878 [Journal]
  32. Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
    An H-V alternating router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:976-991 [Journal]
  33. Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen
    NEWS: a net-even-wiring system for the routing on a multilayer PGA package. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:182-189 [Journal]
  34. Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
    ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:109-135 [Journal]
  35. Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai
    Efficient routability check algorithms for segmented channel routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:735-747 [Journal]
  36. Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen
    Hmap: a fast mapper for EPGAs using extended GBDD hash tables. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:135-150 [Journal]
  37. Pei-Yung Hsiao, Chia-Hsiung Chen, Shin-Shian Chou, Le-Tien Li, Sao-Jie Chen
    A parameterizable digital-approximated 2D Gaussian smoothing filter for edge detection in noisy image. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen
    Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 2007, pp:451-464 [Conf]
  39. Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang
    PSM: an object-oriented synthesis approach to multiprocessor system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:83-97 [Journal]

  40. Compositional Automata Reduction with Non-critical Path Slicing. [Citation Graph (, )][DBLP]


  41. Using XML for VLSI Physical Design Automation. [Citation Graph (, )][DBLP]


  42. An Agile and Low Cost FPGA Implementation of MPEG-2 TS Remultiplexer for CATV Head-End Equipment. [Citation Graph (, )][DBLP]


  43. Performance-energy tradeoffs in reliable NoCs. [Citation Graph (, )][DBLP]


  44. Flow Maximization for NoC Routing Algorithms. [Citation Graph (, )][DBLP]


  45. Parallel implementation of convolution encoder for software defined radio on DSP architecture. [Citation Graph (, )][DBLP]


  46. BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel. [Citation Graph (, )][DBLP]


  47. Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor. [Citation Graph (, )][DBLP]


  48. Edge Detection on the Bayer Pattern. [Citation Graph (, )][DBLP]


  49. Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC. [Citation Graph (, )][DBLP]


  50. Printed circuit board routing and package layout codesign. [Citation Graph (, )][DBLP]


  51. Fluidity concept for NoC: A congestion avoidance and relief routing scheme. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002