The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hiroyuki Kurino: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
    Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. [Citation Graph (0, 0)][DBLP]
    AINA (2), 2004, pp:241-244 [Conf]
  2. Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi
    Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2005, pp:27-32 [Conf]
  3. K. Hirano, T. Ono, Hiroyuki Kurino, Mitsumasa Koyanagi
    A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:333-334 [Conf]
  4. Hiroyuki Kurino, M. Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi
    Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. [Citation Graph (0, 0)][DBLP]
    NIPS, 2000, pp:720-726 [Conf]
  5. Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
    Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2004, pp:564-569 [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002