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Publications of Author

1. Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
   Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. [Citation Graph (0, 0)][DBLP]
   AINA (2), 2004, pp:241-244 [Conf]
   
2. Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi
   Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. [Citation Graph (0, 0)][DBLP]
   ARCS Workshops, 2005, pp:27-32 [Conf]
   
3. K. Hirano, T. Ono, Hiroyuki Kurino, Mitsumasa Koyanagi
   A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1998, pp:333-334 [Conf]
   
4. Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi
   Nanometer design: what hurts next...? [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:242- [Conf]
   
5. Hiroyuki Kurino, M. Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi
   Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. [Citation Graph (0, 0)][DBLP]
   NIPS, 2000, pp:720-726 [Conf]
   
6. Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
   Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. [Citation Graph (0, 0)][DBLP]
   PDCAT, 2004, pp:564-569 [Conf]
   
7. Mitsumasa Koyanagi
   A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. [Citation Graph (0, 0)][DBLP]
   VLSI, 1991, pp:377-386 [Conf]
   
8. 
   Three-dimensional integration technology and integrated systems. [Citation Graph (, )][DBLP]
   
   
9. 
   Development of a High Speed Vision System for Mobile Robots. [Citation Graph (, )][DBLP]
   
   
10. 
    Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. [Citation Graph (, )][DBLP]
    
    
11. 
    A parallel ADC for high-speed CMOS image processing system with 3D structure. [Citation Graph (, )][DBLP]
    
    
12. 
    Heterogeneous integration technology for MEMS-LSI multi-chip module. [Citation Graph (, )][DBLP]
    
    
13. 
    3D integration technology for 3D stacked retinal chip. [Citation Graph (, )][DBLP]
    
    
14. 
    Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. [Citation Graph (, )][DBLP]
    
    
15. 
    10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. [Citation Graph (, )][DBLP]