The SCEAS System
Navigation Menu

Search the dblp DataBase


Shau-Yin Tseng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Chung Lu, Shau-Yin Tseng, Szu-Kai Huang
    A Secure Modular Exponential Algorithm Resists to Power, Timing, C Safe Error and M Safe Error Attacks. [Citation Graph (0, 0)][DBLP]
    AINA, 2005, pp:151-154 [Conf]
  2. Chih-Chung Lu, Shau-Yin Tseng
    Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:277-285 [Conf]
  3. Jia-Ming Chen, Chih-Hao Chang, Shau-Yin Tseng, Jenq Kuen Lee, Wei-Kuan Shih
    Power Aware H.264/AVC Video Player on PAC Dual-Core SoC Platform. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:57-68 [Conf]

  4. Performance and Power Consumption Analysis of DVFS-Enabled H.264 Decoder on Heterogeneous Multi-Core Platform. [Citation Graph (, )][DBLP]

  5. NTPT: on the end-to-end traffic prediction in the on-chip networks. [Citation Graph (, )][DBLP]

  6. The Dynamic Decision Switch for Multiple Pixel Connected Component Labeling Algorithm. [Citation Graph (, )][DBLP]

  7. A Pattern-Search Method for H.264/AVC CAVLC Decoding. [Citation Graph (, )][DBLP]

  8. PAC DSP Core and Application Processors. [Citation Graph (, )][DBLP]

  9. An Efficient DMA Controller for Multimedia Application in MPU Based SOC. [Citation Graph (, )][DBLP]

  10. Fast JPEG Huffman Table Restoring and Decoding for Embedded DSP Implementations. [Citation Graph (, )][DBLP]

  11. Parallel Implementation and Performance Prediction of Object Detection in Videos on the Tilera Many-Core Systems. [Citation Graph (, )][DBLP]

  12. Real-Time Task Replication for Fault Tolerance in Identical Multiprocessor Systems. [Citation Graph (, )][DBLP]

  13. A Low Complexity High Quality Interger Motion Estimation Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP]

  14. Low Complexity High Quality Fractional Motion Estimation Algorithm and Architecture Design for H.264/AVC. [Citation Graph (, )][DBLP]

  15. Parallel 3-Pixel Labeling Method and its Hardware Architecture Design. [Citation Graph (, )][DBLP]

  16. Realization and Optimization of H.264 Decoder for Dual-Core SoC. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002