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Akio Nakata: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takaaki Umedu, Shigeharu Urata, Akio Nakata, Teruo Higashino
    Automatic Decomposition of Java Program for Implementation on Mobile Terminals. [Citation Graph (0, 0)][DBLP]
    AINA, 2005, pp:544-549 [Conf]
  2. Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teruo Higashino
    A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:179-195 [Conf]
  3. Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino
    A real time budgeting method for module-level-pipelined bus based system using bus scenarios. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:37-42 [Conf]
  4. Takaaki Umedu, Yoshiki Terashima, Keiichi Yasumoto, Akio Nakata, Teruo Higashino, Kenichi Taniguchi
    A Language for Describing Wireless Mobile Applications with Dynamic Establishment of Multi-way Synchronization Channels. [Citation Graph (0, 0)][DBLP]
    FME, 2002, pp:607-624 [Conf]
  5. Teruo Higashino, Akio Nakata, Tatsuo Itoh, Kenichi Taniguchi
    Verification of Liveness Property for Communicating FSM's with Conditional Transitions Depending on State Visiting Numbers. [Citation Graph (0, 0)][DBLP]
    FORTE, 1995, pp:433-440 [Conf]
  6. Akio Nakata, Teruo Higashino
    Deriving Parameter Conditions for Periodic Timed Automata Satisfying Real-Time Temporal Logic Formulas. [Citation Graph (0, 0)][DBLP]
    FORTE, 2001, pp:151-168 [Conf]
  7. Akio Nakata, Teruo Higashino, Kenichi Taniguchi
    LOTOS enhancement to specify time constraint among non-adjacent actions using first order logic. [Citation Graph (0, 0)][DBLP]
    FORTE, 1993, pp:451-466 [Conf]
  8. Akio Nakata, Teruo Higashino, Kenichi Taniguchi
    Time-Action Alternating Model for Timed LOTOS and its Symbolic Verification of Bisimulation Equivalence. [Citation Graph (0, 0)][DBLP]
    FORTE, 1996, pp:279-294 [Conf]
  9. Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
    Design and Implementation of FPGA Circuits for High Speed Network Monitors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:393-403 [Conf]
  10. Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
    Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1145-1148 [Conf]
  11. Akio Nakata, Teruo Higashino, Kenichi Taniguchi
    Protocol synthesis from timed and structured specifications. [Citation Graph (0, 0)][DBLP]
    ICNP, 1995, pp:74-0 [Conf]
  12. Atsushi Fukada, Akio Nakata, Junji Kitamichi, Teruo Higashino, Ana R. Cavalli
    A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs. [Citation Graph (0, 0)][DBLP]
    ICOIN, 2001, pp:155-162 [Conf]
  13. Makoto Yamada, Takanori Mori, Atsushi Fukada, Akio Nakata, Teruo Higashino
    A Method for Functional Testing of Media Synchronization Protocols. [Citation Graph (0, 0)][DBLP]
    ICOIN (2), 2002, pp:539-550 [Conf]
  14. Teruo Higashino, Akio Nakata, Kenichi Taniguchi, Ana R. Cavalli
    Generating Test Cases for a Timed I/O Automaton Model. [Citation Graph (0, 0)][DBLP]
    IWTCS, 1999, pp:197-214 [Conf]
  15. Akio Nakata, Teruo Higashino, Kenichi Taniguchi
    Protocol Synthesis from Context-Free Processes Using Event Structures. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1998, pp:173-180 [Conf]
  16. Tomoya Kitani, Yoshifumi Takamoto, Keiichi Yasumoto, Akio Nakata, Teruo Higashino
    A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:437-446 [Conf]
  17. Keiichi Yasumoto, Takaaki Umedu, Hirozumi Yamaguchi, Akio Nakata, Teruo Higashino
    Protocol animation based on event-driven visualization scenarios in real-time LOTOS. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2002, v:40, n:5, pp:639-663 [Journal]
  18. Akio Nakata, Tadaaki Tanimoto, Suguru Sasaki, Teruo Higashino
    A Timed Failure Equivalence Preserving Abstraction for Parametric Time-interval Automata. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2006, v:17, n:4, pp:833-850 [Journal]
  19. Takanori Mori, Hirotaka Otsuka, Nobuo Funabiki, Akio Nakata, Teruo Higashino
    A test sequence generation method for communication protocols using the SAT algorithm. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2003, v:34, n:11, pp:20-29 [Journal]
  20. Takanori Mori, Akio Nakata, Teruo Higashino
    A Method for Designing Multimedia Protocols using Both Parametric Model Checking and Functional Testing. [Citation Graph (0, 0)][DBLP]
    Stud. Inform. Univ., 2004, v:3, n:2, pp:231-0 [Journal]

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