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Makoto Ikeda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giuseppe De Marco, Makoto Ikeda, Tao Yang, Leonard Barolli
    Experimental Performance Evaluation of a Pro-Active Ad-hoc Routing Protocol in Out- and Indoor Scenarios. [Citation Graph (0, 0)][DBLP]
    AINA, 2007, pp:7-14 [Conf]
  2. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:149-154 [Conf]
  3. Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
    Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:323-324 [Conf]
  4. Jian Qiao, Makoto Ikeda, Kunihiro Asada
    Finding an optimal functional decomposition for LUT-based FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:225-230 [Conf]
  5. Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada
    A binary image sensor with flexible motion vector detection using block matching method. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:21-22 [Conf]
  6. Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada
    A smart position sensor for 3-D measurement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:21-22 [Conf]
  7. Yusuke Oike, Makoto Ikeda, Kunihiro Asada
    Design of real-time VGA 3-D image sensor using mixed-signal techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:523-524 [Conf]
  8. Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
    A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:3-4 [Conf]
  9. Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
    Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:166-171 [Conf]
  10. Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
    On-chip 8GHz non-periodic high-swing noise detector. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:670-671 [Conf]
  11. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Timing-driven cell layout de-compaction for yield optimization by critical area minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:884-889 [Conf]
  12. Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
    Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:147-148 [Conf]
  13. Zhicheng Liang, Makoto Ikeda, Kunihiro Asada
    Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:81-86 [Conf]
  14. Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
    Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:87-95 [Conf]
  15. Makoto Ikeda, Kunihiro Asada
    A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:546-550 [Conf]
  16. Jian Qiao, Makoto Ikeda, Kunihiro Asada
    Optimum Functional Decomposition for LUT-Based FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:555-564 [Conf]
  17. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Exact minimum-width transistor placement without dual constraint for CMOS cells. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:74-77 [Conf]
  18. Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
    Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:368-371 [Conf]
  19. Makoto Ikeda, Leonard Barolli, Giuseppe De Marco, Arjan Durresi, Akio Koyama, Mimoza Durresi
    Evaluation of a Network Extraction Topology Algorithm for Reducing Search Space of a GA-based Routing Approach. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2006, pp:54- [Conf]
  20. Yusuke Yachide, Yusuke Oike, Makoto Ikeda, Kunihiro Asada
    Real-time 3-D measurement system based on light-section method using smart image sensor. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:1008-1111 [Conf]
  21. Makoto Ikeda, Leonard Barolli, Shohei Ohba, Genci Capi, Akio Koyama, Mimoza Durresi
    A CAC and Routing Framework for Multimedia Applications in Broadband Networks Using Fuzzy Logic and Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2005, pp:648-654 [Conf]
  22. Yusuke Oike, Makoto Ikeda, Kunihiro Asada
    High-speed position detector using new row-parallel architecture for fast collision prevention system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:788-791 [Conf]
  23. H. Yoshida, H. Yamaoka, M. Ikeda, K. Asada
    Logic synthesis for PLA with 2-input logic elements. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:373-376 [Conf]
  24. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:377-380 [Conf]
  25. Makoto Ikeda, Hideyuki Aoki, Kunihiro Asada
    DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:305-308 [Conf]
  26. Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada
    Computational Cost Reduction in Extracting Inductance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:179-184 [Conf]
  27. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:776-781 [Conf]
  28. Makoto Ikeda, Kunihiro Asada
    Standard design flows of Logic LSIs in Japanese universities and VDEC. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:8-9 [Conf]
  29. Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada
    Comparative Study On Verilog-Based And C-Based Hardware Design Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:41-42 [Conf]
  30. Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada
    Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:166-171 [Conf]
  31. Makoto Ikeda, Leonard Barolli, Akio Koyama, Arjan Durresi, Giuseppe De Marco, Jiro Iwashige
    Performance evaluation of an intelligent CAC and routing framework for multimedia applications in broadband networks. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 2006, v:72, n:7, pp:1183-1200 [Journal]
  32. Tao Yang, Giuseppe De Marco, Makoto Ikeda, Leonard Barolli
    Impact of radio randomness on performances of lattice wireless sensors networks based on event-reliability concept. [Citation Graph (0, 0)][DBLP]
    Mobile Information Systems, 2006, v:2, n:4, pp:211-227 [Journal]
  33. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  34. Makoto Ikeda, Giuseppe De Marco, Leonard Barolli
    A Simple Statistical Methodology for Testing Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    NBiS, 2007, pp:1-10 [Conf]
  35. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:716-720 [Journal]

  36. A BAT in the Lab: Experimental Results of New Link State Routing Protocol. [Citation Graph (, )][DBLP]


  37. Performance Analysis of OLSR and BATMAN Protocols Considering Link Quality Parameter. [Citation Graph (, )][DBLP]


  38. Performance Evaluation of Wireless Sensor Networks for Mobile Sink Considering Consumed Energy Metric. [Citation Graph (, )][DBLP]


  39. Mobility Effects of Wireless Multi-hop Networks in Indoor Scenarios. [Citation Graph (, )][DBLP]


  40. Circuit design using stripe-shaped PMELA TFTs on glass. [Citation Graph (, )][DBLP]


  41. Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. [Citation Graph (, )][DBLP]


  42. Measurement of power supply noise tolerance of self-timed processor. [Citation Graph (, )][DBLP]


  43. All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. [Citation Graph (, )][DBLP]


  44. Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. [Citation Graph (, )][DBLP]


  45. Routing Efficiency of AODV and DSR Protocols in Ad-Hoc Sensor Networks. [Citation Graph (, )][DBLP]


  46. Network energy consumption in ad-hoc networks under different radio models. [Citation Graph (, )][DBLP]


  47. A Simulation System for Routing Efficiency in Wireless Sensor-Actor Networks: A Case Study for Semi-automated Architecture. [Citation Graph (, )][DBLP]


  48. Performance Behavior of AODV, DSR and DSDV Protocols for Different Radio Models in Ad-Hoc Sensor Networks. [Citation Graph (, )][DBLP]


  49. An Effective Topology Extraction Algorithm for Search Reduction Space of a GA-based QoS Routing Method in Ad-Hoc Networks. [Citation Graph (, )][DBLP]


  50. Experimental and Simulation Evaluation of OLSR Protocol for Mobile Ad-Hoc Networks. [Citation Graph (, )][DBLP]


  51. Performance Evaluation of Two Search Space Reduction Methods for a Distributed Network Architecture. [Citation Graph (, )][DBLP]


  52. Performance Analysis of OLSR Protocol for Wireless Sensor Networks and Comparison Evaluation with AODV Protocol. [Citation Graph (, )][DBLP]


  53. Performance Evaluation of a MANET Tested for Different Topologies. [Citation Graph (, )][DBLP]


  54. A Case Study of Event Detection in Lattice Wireless Sensor Network with Shadowing-Induced Radio Irregularities. [Citation Graph (, )][DBLP]


  55. A Distributed QoS Routing and CAC Framework: Performance Evaluation of Its SSRA and InterD Agents. [Citation Graph (, )][DBLP]


  56. Performance Evaluation of a Wireless Sensor Network Considering Mobile Event. [Citation Graph (, )][DBLP]


  57. Performance Evaluation of Link Quality Extension in Multihop Wireless Mobile Ad-hoc Networks. [Citation Graph (, )][DBLP]


  58. Performance Evaluation of Wireless Sensor Networks for Different Radio Models Considering Mobile Event. [Citation Graph (, )][DBLP]


  59. Mobility Effects on the Performance of Mobile Ad hoc Networks. [Citation Graph (, )][DBLP]


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